This invention relates to a method for fabricating insulated gate field effect transistor (IGFET) integrated circuits, and more particularly to a fabrication method which arranges device features on a chip for a random-logic circuit in a manner compatible with convenient layout of the chip.
IGFET integrated circuits are well known in the art. Such circuits are normally fabricated with p-channel, n-channel or complementary channel versions of the metal-oxide-semiconductor technology; such version being commonly referred to as PMOS, NMOS, and CMOS, respectively. Each of these IGFET technologies has the capability for fabricating large scale integration (LSI) circuits having as many as tens of thousands of transistors on a single substrate chip of silicon or sapphire.
A significant part of the cost of manufacturing an LSI circuit is in the layout of the chip. In the layout process device features which are to be formed on a chip through a series of processing steps are arranged to correspond to a desired circuit configuration. Such a process can be difficult and time consuming particularly in the case of the larger LSI circuits where as many as hundreds of thousands of device features forming transistors and circuit interconnections must be arranged on a chip in a densely packed manner.
Achieving a high packing density of device features is a major objective in the chip fabrication process. Inasmuch as the manufacturing yield of a chip decreases rapidly with increasing chip area it is important from the standpoint of lower manufacturing cost manufacture to keep the chip area for a given circuit as small as practicable. However, in many cases achieving a high packing density increases the time required for chip layout, and, therefore, the chip design cost.
For circuits which have a high degree of repetitiveness, such as a random access memory (RAM), a read only memory (ROM), a programmable logic array (PLA) and the like chip layout is greatly simplified by the fact that the chip features for such circuits occur repetitively in a regular ordered array. For example in the case of a RAM having several thousand storage cells the layout of a cell is performed only once and the same cell configuration is repeated at each storage cell location in an ordered and regular array.
However, for circuits having little or no repetitiveness, often referred to as random-logic circuits, the chip layout process using prior art techniques can be difficult and time consuming. Some LSI circuits, such as microprocessors have on the same chip portions which are repetitive (e.g., a PLA) and portions which are random-logic (e.g., an arithmetic logic unit).
The most commonly used method for chip layout of a random-logic circuit is for a chip designer to place device feature individually or in groups according to his judgement to achieve the desired circuit and a high packing density. Because this method, which is sometimes referred to as the "handpacking" method, involves no systematic steps or rules, the packing density which is achieved for a given circuit depends largely on the skill of the chip designer and the amount of time spent in making the layout. Therefore, a problem with the fabrication of random-logic LSI circuits is the difficulty and expense of chip layout using the "handpacking" technique.
Frequently, to expedite the chip layout process for a large LSI circuit the layout task is divided among several chip designers who each perform layout on a different portion of the chip. Where the "handpacking" method is used it is difficult to predetermine the positions of signal lines and of the areas and shapes of the portions by the different chip designers. Therefore, problems often arise when the different portions of the chip are finally combined and the time savings derived from dividing the layout task is offset by increased chip area usage caused by complexities of interconnection between the different portions of the chip.
Another problem related to the layout of an LSI chip is the checking for errors once a layout is completed. Not only must the device features be properly placed to achieve a functional circuit but the sizes of device features and the spacings between device features must be within permissable tolerances as required by the particular technology being used to fabricate the circuit. The usual method for error checking is by visual inspection of the completed layout. The method is extremely tedious and unreliable for a large layout made by the "handpacking" method. Error checking by visual inspection is much less tedious and more reliable for circuits having order and regularity.
A known prior art technique for reducing the cost of chip layout and error checking for random-logic LSI circuits is the standard cell method for chip layout. In this method the layouts for all the basic logic elements (i.e., gates, flip-flops, etc.) called standard cells which have been previously made, are available in a "library" of standard cells. In the layout process for a circuit those standard cells which are required by the circuit are placed in spaced apart rows deployed over the chip area. The spacings between the rows serve as "wiring channels" for conductor paths interconnecting the various standard cells. Placement of the cells in the rows are selected to minimize the areas of the "wiring channels". Error checking in chip layouts by the standard cell method is simplified because the standard cells themselves are generally proven patterns which need no further checking and the interconnections of the circuit which are confined to "wiring channels" are easily traced. Although the standard cell method provides large time savings in chip layout and error checking, it is deficient from the standpoint of chip area usage. Inasmuch as the interconnections of a standard cell chip layout are confined to "wiring channels" and restricted from the standard cell regions chip area usage is far from being optimal. For a given random-logic circuit, a standard cell chip layout may require as much as ten to twenty percent more chip area than "handpacked" layout of the same circuit. Thus, there is clearly a need for a rapid and systematic method for chip layout of a random-logic circuit which provides efficient usage of chip area and which facilitates checking for layout errors. Finally, it is important that the chip layout be compatible with facile fabrication of the chip.